A modern silicon semiconductor integrated circuit (IC) can have millions of component devices such as transistors in a complex arrangement on a single die. This integration has led to advancements in IC fabrication technologies as well advancements in design automation tools.
Semiconductor IC manufacturers employ production electrical testing to validate that their ICs function correctly. With such large numbers of component devices, complex arrangements of the devices, and a multitude of functionalities, it becomes more difficult and problematic for semiconductor IC manufacturers to perform this validation. This has resulted in an escalating cost to the manufacturers to perform production electrical testing.
While the cost to manufacture silicon ICs can be separated into the cost of the silicon, the cost of the package, and the cost of testing, the escalating cost of production electrical testing has become a significant factor in the cost to manufacture.
Manufacturers employ various designs in their ICs to reduce the cost of testing. Typically, these designs are referred to in the industry as design-for-test (DFT), design-for-testability (DFT), or built-in-self-test (BIST). For digital circuits, great strides have been made in the industry with DFT designs. For example, defect oriented testing using a structural test paradigm is well known. With this type of DFT, no direct attempt is made to test the overall functionality. Instead, this type of testing focuses on testing for defects in the low-level building blocks (e.g., logic gates) and their interconnectivity. If such testing determines there is no defect, correct functioning of the entire circuit is assumed.
For analog circuits and mixed-signal circuits (i.e., circuits that use both analog and digital circuitry), circuit performance is sensitive to manufacturing process variations. Variations in the process can degrade the performance of such circuits. Even if low-level building blocks (e.g., transistors) are free from manufacturing defects, the circuit may still have unacceptable performance. Therefore, for analog and mixed-signal circuits, circuit-specific performance test DFTs have been proposed. For example, DFTs for analog-to-digital converters and for phase-locked loops have been proposed. However, these known DFTs are not adaptable to a wide variety of circuits.
To address this problem for analog and mixed-signal circuits, the industry has found some utility in measuring DC (non-time-varying or average) voltages of critical nodes within the circuit. If testing an integrated circuit determines that the critical nodes on an integrated circuit have DC voltages that substantially match those of a known good integrated circuit, correct functioning of the tested integrated circuit is assumed. One method that has been suggested for measuring DC voltages on an integrated circuit is to use a scanning scheme based on the IEEE 1149.4 standard. This scheme allows external equipment to access IC internal nodes through a test bus. The bus uses pins on the IC package to provide the access required and the measurement is made using external equipment. One problem with this method is that the number of nodes that can be accessed and measured at one time is limited by the number of pins used for the test bus and/or by the limitations of external equipment. Scanning allows the pins to access different nodes at different times but this requires more test time, which may result in unacceptably long total test times for an IC.
Another DFT method that has been proposed for measuring DC voltages of critical nodes is to employ an on-chip analog-to-digital converter or encoder (ADC) to convert a critical node DC voltage to a digital value. This tends to speed up the measurement process compared to using external equipment. Precision and accuracy of the ADC are important considerations with this method. A problem with this method is that an ADC can only measure the voltage of one critical node at a time. Thus, switching the ADC input sequentially to all of the critical nodes can lead to an excessive time for circuit testing. Of course, multiple ADCs could be used in parallel, but integrating these ADCs would significantly increase the area of the IC silicon required to accommodate the ADCs and, thus, increase the cost of the silicon.